The present invention is generally directed to structures and methods for controlling the thickness of the gap between an electronic circuit chip and a lid, heat sink or other cooling mechanism. More particularly, the present invention is directed to a system in which the size of the gap between the circuit chip and the lid or heat sink is controlled and even more particularly controlled so that this gap is made to be as small as possible without deleteriously effecting the assembly process or chip integrity. Even more particularly, the present invention is directed to a system for controlling the thickness of thermal paste material disposed between either a single chip or multi-chip module and its lid or cover.
As device integration levels keep on increasing, the demand for a more efficient solution to the cooling of high power electronic circuit chips becomes an even more important ingredient in achieving required system performance. The use of thermal paste or gel to cool single chip or multi-chip modules is highly desirable because of its simplicity and high thermal performance. Thermal pastes are also not impacted by small particle contamination; hence, module assembly can be done in non-clean room environments, which is a factor in helping to reduce module assembly costs. Furthermore, the compliance of thermal pastes allows them to absorb mechanical tolerances that are associated with chip height and hardware variations.
An additional method for providing efficient cooling for electronic circuit chips is the use of solder between the chip and its corresponding module lid. In such cases, the chip backside is metallized and solder is wetted to both lid and chip surfaces such that when the solder is reflowed, a joint is achieved between the chip and the lid. Solder has a thermal conductivity about ten times the thermal conductivity of the best thermal paste available; hence it provides a significant improvement in thermal performance over thermal pastes. However, the compliance advantages of thermal pastes can be achieved while simultaneously improving thermal conductive characteristics through control of paste thickness in the gap between chip and lid.
It is known that it is desirable for electronic devices to operate at low temperatures for enhanced performance and reliability. This is particularly true for CMOS devices where a 10.degree. C. reduction in temperature produces approximately a 2% gain in system speed.
To a first order of approximation, the temperature of the chip is given by the following one-dimensional equation: EQU T.sub.chip =T.sub.air +P.sub.chip.times.R.sub.int +P.sub.mod.times.R.sub.ext
In the case of a single chip module, the module power equals the chip power, and the above equation simplifies to: EQU T.sub.chip =T.sub.air +P.sub.chip.times.(R.sub.in +R.sub.ext)
In the above equations, R.sub.in represents the internal thermal resistance of the module, that is the resistance from the chip up through the thermal paste to the module lid, whereas R.sub.ext represents the thermal resistance external to the module, that is the lid-to-heat sink interface plus the heat sink resistance, including air heating effects.
The internal thermal resistance is composed of three resistances in series: EQU R.sub.in =R.sub.chip +R.sub.paste +R.sub.lid
Since the lid is typically made of a high thermal conductivity material such as aluminum, the thermal paste resistance is the largest contributor to the internal thermal resistance, R.sub.in. Reduction of the thermal paste resistance is therefore a significant factor in reducing the overall device temperature.
The thermal resistance of paste is given by the following equation: EQU R.sub.paste =L.sub.gap /(K.sub.paste.times.A.sub.chip)
where L.sub.gap is thickness of the paste between the chip and module lid, K.sub.paste is the paste thermal conductivity, and A.sub.chip is the area of the chip. It is clear from this expression that reduction of the paste thermal resistances, R.sub.paste, can only be accomplished via either (i) reduction of the paste gap size and/or (ii) an increase in the thermal conductivity of the thermal paste.
Current designs use the compliance of the thermal paste to accommodate variations in the thermal paste gap. The tolerances are mainly driven by the tolerances on the chip thickness, tolerances for the chip solder balls and by tolerances on the hardware ans substrate. The statistical variations of these tolerances are typically between .+-.0.003 to 0.004 inches. Since the thermal paste "squeeze force" goes up exponentially as the paste is squeezed into very small gaps, that is into gaps under 0.003 inches, any single chip or multi-chip module should be designed to achieve a thermal paste gap of at least 0.007 inches under normal conditions. The statistical maximum paste gap therefore becomes 0.010 to 0.011 inches.
If solder is used between the chip and the module lid, it is still necessary to consider the same type of design tolerances as with thermal paste alone. While paste gap control for solder is not as critical to thermal performance, the apparatus and method disclosed herein for controlling the thermal paste gap is also employable to achieve optimum solder fillet shape since this can have an impact on solder reliability during thermal cycling. Accordingly, via the present invention, thermal paste cooling becomes more efficient and the solder thermal interface becomes more reliable. (It is noted that it is the higher thermal conductivity of solder which tends to reduce design tolerance problems as compared with the use of thermal paste alone).
The present invention provides a structure and a method for controlling the gap between the chip and a module lid while still maintaining the chip and its interconnect structure within a sealed environment. The sealed package is desirable to prevent moisture from contacting the chip, particularly over long periods of time. Accordingly, the improved use of thermal paste cooling, as employed in the present invention becomes more efficient and even solder based cooling systems become even that much more reliable.